Experiments for Accelerating IEEE 802.11i on Cyclone II FPGA
نویسنده
چکیده
This paper presents hardware solutions for accelerating IEEE 802.11i. Several experiments were applied on the low-cost Cyclone II FPGA by using various architectures with different number of threads. The FPGA offloads the process of AES encryption from the master CPU. In addition, it offers the possibility of using several threads to run the AES encryption. Different optimizations have been applied on the hardware architecture of AES and on the basic unit of AES, in order to satisfy different constraints in terms of latency, area occupation and speed. Their performances are compared to AES software implemented on a NIOS II processor. A strong focus is devoted for the achievement of high throughput, which is required to support security requirements for the high bandwidth applications.
منابع مشابه
FPGA Implementation AES for CCM Mode Encryption Using Xilinx Spartan-II
This paper discusses a possible FPGA implementation of the AES algorithm specifically for the use in CCM Mode Encryption. CCM Mode encryption is a proposed standard to be used and the security backbone behind the new IEEE Std. 802.11i. CCM currently spends most the computation power performing the AES algorithm. This paper investigate the possibility of creating an off-chip AES system for CCM s...
متن کاملDevelopment and Implementation of Novel Data Compression Technique for Accelerate DNA Sequence Alignment Based on Smith–Waterman Algorithm
Abstract— This paper presents the development and implementation of high performance accelerating and optimization technique for DNA sequences alignment algorithm. The scope of the paper focuses on speed optimization and memory reduction of the existing algorithm on initialization module. The novel development and implementation of the optimization using data compression technique for accelerat...
متن کاملAn Algorithm for the ηT Pairing Calculation in Characteristic Three and its Hardware Implementation
In this paper, we propose a modified ηT pairing algorithm in characteristic three which does not need any cube root extraction. We also discuss its implementation on a low cost platform which hosts an Altera Cyclone II FPGA device. Our pairing accelerator is ten times faster than previous known FPGA implementations in characteristic three.
متن کاملAn FPGA-based AES-CCM Crypto Core For IEEE 802.11i Architecture
The widespread adoption of IEEE 802.11 wireless networks has brought its security paradigm under active research. One of the important research areas in this field is the realization of fast and secure implementations of cryptographic algorithms. Under this work, such an implementation has been done for Advanced Encryption Standard (AES) on fast, efficient and low power Field Programmable Gate ...
متن کاملDesign and Implementation of Low Complexity Router for 2D Mesh Topology using FPGA
Modern platform Field Programmable Gate Arrays provide larger gate count with increased performance. This feature allows realization of System On Chip on modern FPGAs. When the number of cores increases, the communication demands between cores also increases in SoCs. Hence, Network On Chip has been proposed, to meet out the challenges between the cores. In this paper, a design of low cost, low ...
متن کامل